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Vertical Conductive Structure
A new interconnect technology

 

VeCS is developed as a need for a more intelligent PCB technology that reduces layercount and improves signal integrity without the need got sequential technologies as Anylayer.

 

VeCS technology can be build under license by any PCB shop and does not require capital investments (asuming capability is present to build medium to high technology circuits). We only change the sequence of process steps and create a revolution in circuit board technology.

 

 

In the table below we made a comparison between Through holes, VeCS and Anylayer technology. It has to be said that Anylayer technology is much more expensive as it requires a high number of lamination, drilling and plating cycles to build up a reasonable numbers of layers. In additional the material thickness that can be used are limited and typically 2,8 mil / 70 micron.

 

The routing channel in a VeCS design is different then in a traditional through hole or Microvia/Anylayer design. We combine routing channels to create a better utilisation of the channel. We have a very high utilisation of the channel due to the wider channel (more trace to trace isolations then trace to pad isolations). To have a 1:1 comparison we to have of the number of traces for the improvement.

 

You see in comparison that Anylayer and VeCS are close for the small pitch devices, the advantage for VeCS comes from the freedom in dielectric types and thicknesses that can be used and no limitation in layer counts.

 

 

 

 

 

 

 

  

 

 

 

 

 

 

VeCS is the acronym for Vertical Conductive Structure and is a new interconnect technology following and adding to the known HDI / Microvia technology without the limitations of HDI. Semiconductor packaging technology is driving the circuit board technology and with the pitches getting smaller and the pin-count more dense HDI is not the solution. Sequential lamination and microvias are a technical solution but not from a cost perspective.