VeCS Design Rules
VeCS is a technology that can be applied in many different forms and shapes. The VeCS design rules as listed below are generic and we advice you to contact Nextgin for the lastest design rules for the board supplier(s) you are working with.
Example of VeCS shapes and cross sections
The following images show more advanced VeCS shapes were we use our so called shielded VeCS applications.
The image below shows a STEP file of an embedded VeCS slot with a longer shield from the side to minimize crosstalk to adjacent traces. This shows one of many options with VeCS. Also shown is that the different pair is connected using a Microvia from layer 1 to layer 2. This can be applied for example in cases where there is a dense outlayer pattern and the isolation to the VeCS is compromised.
At high frequencies the shifting of the GND level can disrupt the function of the circuit. We there for prefer at high performance circuits to connect the bottom GND below the signal layer in the same VeCS to eliminate or minimize GND shift effects.
Routing Channel usage
The following table is showing the routing channel widths compared between PTH, PTH backdrilled and VeCS as function of different pitches.
VeCS can be used for connectors as well. This is not yet characterized in terms of pressfit force characteristics.
If you want more details please contact us on if you have interest in starting to work with VeCS.